Sam L
Co-Founder & CEO at Lyster
Stockholm, Sweden
Summary
🤩
Rockstar🎓
Top SchoolSam L is a driven engineering leader and founder with 11 years of experience building embedded and software systems, now leading Lyster as Co-Founder & CEO from Stockholm. He combines hands-on technical depth—from a BSc in Electrical Engineering and an MSc in Embedded Systems to doctoral research—with practical leadership roles at Accenture and Netlight. Sam has contributed to open-source hardware tooling, notably implementing and hardening the PMP plugin in the FPGA-friendly VexRiscv RISC-V core, reflecting deep knowledge of memory protection and low-level CPU design. Comfortable switching between research, engineering and management, he has a track record of turning complex, safety-critical concepts into robust implementations. Colleagues would describe him as a pragmatic problem solver who brings academic rigor to product-focused teams.
10 years of coding experience
4 years of employment as a software developer
Master of Science (M.Sc.), Embedded Systems, Master of Science (M.Sc.), Embedded Systems at KTH Royal Institute of TechnologyBachelor of Science (B.Sc.), Electrical Engineering, Bachelor of Science (B.Sc.), Electrical Engineering at Northeastern University
Swedish, English
Github Skills (6)
risc-v10
spinalhdl10
verilog10
fpga9
hdl9
soc8
Programming languages (10)
Github contributions (5)
SpinalHDL/VexRiscv
Oct 2020 - Jun 2021
A FPGA friendly 32 bit RISC-V CPU implementation
Role in this project:
Back-end Developer
Back-end DeveloperContributions:32 commits, 6 PRs, 62 comments in 7 months
Contributions summary:Sam implemented and refined the PMP (Protected Memory Protection) plugin within the VexRiscv CPU project. Their initial contributions focused on the creation of the PMP plugin and subsequent enhancements to enable register locking, ensuring that PMP configurations are preserved. Further work involved improvements to the FSM to improve access controls. The commits demonstrate an understanding of the RISC-V architecture and memory protection mechanisms.
cpuverilogrisc-vvhdlriscv
lindemer/VexRiscv
Oct 2020 - Jun 2021
A FPGA friendly 32 bit RISC-V CPU implementation
Contributions:112 pushes, 13 branches in 8 months
risc-vcpu32-bitriscbit
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