Samuel Riedel
Senior Hardware Software Engineer at lowRISC CIC
Switzerland
Summary
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Rockstar🎓
Top SchoolSamuel Riedel is a Senior Hardware/Software Engineer based in Switzerland with eight years of experience bridging RTL hardware design and low-level software. After completing a PhD-equivalent trajectory at ETH Zürich and long involvement with the PULP ecosystem, he now works at lowRISC applying deep expertise in SystemVerilog and RISC-V microarchitecture. His open-source contributions include refining AXI SystemVerilog IP and adding AMO support to the CV32E40P RISC-V core, showing strength in both protocol-level verification and ISA-level decoder design. Samuel pairs academic rigor with practical product impact—previous projects include FPGA data pipelines and Linux driver stacks for high-speed cameras—making him adept at shipping complex embedded systems from silicon interface to software.
8 years of coding experience
1 year of employment as a software developer
Matura, Matura at Kantonsschule RychenbergExchange Semester, Exchange Semester at Imperial College LondonDoctor of Science, Electrical Engineering and Information Technology, Doctor of Science, Electrical Engineering and Information Technology at ETH ZürichCambride Advanced English (CAE), Cambride Advanced English (CAE) at EF Executive Language Institute
German, English, French
Github Skills (15)
rt10
hdl10
fpga10
risc-v10
embedded10
verilog10
ax10
systemverilog10
sys10
hardware10
computer-architecture10
axi410
digital-design9
ip9
asic7
Programming languages (6)
Github contributions (5)
pulp-platform/axi
Mar 2019 - Mar 2022
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:5 reviews, 23 commits, 8 PRs in 3 years
Contributions summary:Samuel primarily contributed to SystemVerilog modules within the AXI framework. Their commits focused on refining the AXI interface, including fixes and updates to modules like `axi_lite_to_apb`, `axi_demux`, and `axi_id_remap`. These changes involved correcting interface versions, fixing functional errors, and enhancing the AXI simulation memory module with monitoring capabilities, demonstrating a focus on hardware design and verification.
rtlsystemverilogvlsifpgaaxi4
openhwgroup/cv32e40p
Mar 2018 - Jun 2019
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:9 commits, 4 pushes, 2 branches in 1 year 3 months
Contributions summary:Samuel focused on implementing Atomic Memory Operations (AMO) support within the CV32E40P RISC-V processor's decoder and associated modules. This involved adding new instructions, defining AMO-related parameters, and modifying the decoder to handle these atomic operations. The contributions included modifications to the `riscv_decoder.sv`, `riscv_id_stage.sv`, `riscv_core.sv`, and `riscv_load_store_unit.sv` files, as well as defining new instructions within `riscv_defines.sv` and expanding the tracer to support the A-extension.
risc-vcpupulpuvmriscv
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