Quality Engineering, Staff Engineer at Synopsys Inc
Portland, Oregon Metropolitan Area United States
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Summary
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Senior
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Sandeep Dey is a quality engineering staff engineer with 13 years in semiconductor EDA, specializing in mask validation (OPC, ILT) and pattern analysis for VLSI using C++ and Python. He holds a PhD in Computational Geometry and VLSI CAD from USI, contributed an L∞ segment Voronoi implementation to CGAL, and co-authored multiple award-winning papers on line-segment Voronoi diagrams. At Synopsys and Intel he has translated geometric research into production-grade lithography validation tools and test automation. His background spans academic research, industrial R&D, and teaching, giving him a rare mix of formal algorithmic rigor and pragmatic software delivery. Based in Portland, he brings deep expertise in algorithms, data structures, and geometric predicates applied to high-stakes chip manufacturing problems.
13 years of coding experience
11 years of employment as a software developer
M.Tech Computer Science, M.Tech Computer Science at Indian Statistical Institute, Kolkata
BSc Chemistry(H), BSc Chemistry(H) at Malda College
B.Tech Electronics and Communication, B.Tech Electronics and Communication at Kalyani Government Engineering College
M. Tech Computer Science, M. Tech Computer Science at West Bengal University of Technology, Kolkata
Kendriya Vidyalaya Sangathan
Doctor of Philosophy (Ph.D.) Computer Science, Doctor of Philosophy (Ph.D.) Computer Science at USI Università della Svizzera italiana
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Sandeep Dey - Quality Engineering, Staff Engineer at Synopsys Inc