Sandeep Rajendran
Hardware Verification Engineer
California, United States
Summary
🤩
Rockstar🎓
Top SchoolSandeep Rajendran is a Hardware Verification Engineer based in California with seven years of experience validating complex SoC designs and improving hardware stability. At SiFive since 2018, he focuses on verification and has hands-on experience addressing interrupt logic, reset behaviors, and glitch assertions to harden real-world RISC-V implementations. His open-source contributions to the widely used Rocket Chip Generator show practical improvements—adding fuzzing controls, clarifying plusargs, and fixing event covers—that reflect both system-level thinking and attention to developer ergonomics. Earlier roles building embedded audio transmission systems and Raspberry Pi–based autonomous navigation prototypes give him a strong background in embedded systems and applied image processing. He holds a B.Tech in ECE from NIT Karnataka and a Master’s in Computer Engineering from NC State, blending academic rigor with production verification practice. Colleagues would describe him as detail-oriented and pragmatic, with a knack for translating subtle hardware bugs into robust design fixes.
7 years of coding experience
Master's degree, Computer Engineering, Master's degree, Computer Engineering at North Carolina State UniversityGEMS EducationBachelor of Technology (B.Tech.), Electronics and Communications Engineering, Bachelor of Technology (B.Tech.), Electronics and Communications Engineering at National Institute of Technology Karnataka
English, Hindi, Tamil
Github Skills (9)
chisel10
rt10
risc-v10
chip810
generator10
scala10
sys9
embedded9
verilog8
Programming languages (2)
Github contributions (5)
chipsalliance/rocket-chip
Nov 2018 - May 2020
Rocket Chip Generator
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:13 commits, 13 PRs, 9 pushes in 1 year 5 months
Contributions summary:Sandeep made several contributions to the Rocket Chip Generator, primarily focused on improving the design's stability and functionality. Their work included fixing event covers, adding options to disable fuzzing, and renaming plusargs for better clarity. They also addressed issues related to reset values and glitch assertions within the interrupt handling logic, demonstrating an understanding of hardware design principles.
rtlriscvchipchiselscala
SandeepRajendran/riscv-test-env
Oct 2020 - Oct 2020
Contributions:1 push in 1 day
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