Sanggi Do is a Staff Engineer at Samsung Foundry with nine years’ experience designing and verifying standard cell libraries for advanced process nodes. He combines hands-on RTL/HDL expertise (Verilog, SystemVerilog) with strong software tooling skills (C++, Python, Tcl, Unix) to bridge digital IC design and EDA flows. His background spans academic research at UNIST, POSTECH and UCSD in SoC/VLSI CAD to production library engineering, giving him both R&D depth and foundry-grade delivery experience. Known for pragmatic verification strategies, he focuses on buildable, automation-first solutions that reduce tapeout risk. Sanggi’s military engineering service and cross-institution collaborations suggest he excels in disciplined, cross-functional teams and in scaling research into manufacturable IP.
9 years of coding experience
4 years of employment as a software developer
Master's degree, Electrical Engineering, Master's degree, Electrical Engineering at Ulsan National Institute of Science and Technology
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