Sanjay Shreedharan is a Physical Design CAD Engineer at Apple with a decade of engineering experience bridging embedded firmware, hardware design, and VLSI physical design. He holds a Master's in Computer Engineering from Arizona State University where he designed and tape-out-capable RTL for a novel Single Event Transient measurement testchip, combining hands-on RTL, scan/Vernier techniques, and mixed-signal test planning. His toolset spans Cadence/ Synopsys flows, Calibre/ICV, HSPICE, gem5 and scripting in Python/Tcl, complemented by firmware expertise in C/C++ and low-power PCB design. Prior roles include embedded systems development—battery-optimized sensor products and P2P multimedia stacks—and logic design internships, reflecting a rare cross-domain fluency from PCB to GDSII. Based in Austin, he seeks to apply deep physical-design CAD skills to complex SoC and ASIC challenges.
10 years of coding experience
4 years of employment as a software developer
Bachelor of Engineering (B.E.) Electrical and Electronics Engineering, Bachelor of Engineering (B.E.) Electrical and Electronics Engineering at SSN College Of Engineering
Master's degree Computer Engineering, Master's degree Computer Engineering at Arizona State University
High School, High School at DAV Boys Senior Secondary School, Gopalapuram
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Sanjay Shreedharan - Physical Design CAD Engineer at Apple