Sanjeev Singh
Senior Design Verification Engineer
Apex, North Carolina, United States
Summary
👤
Senior🎓
Top SchoolSanjeev Singh is a Senior Design Verification Engineer with two decades of ASIC verification experience and a 14-year track record in senior engineering roles across NVIDIA, Apple, and Juniper Networks. He specializes in UVM testbenches, formal verification, and multi-chip/system-level simulation, having driven multiple first-time silicon successes and led verification for complex packet processors, memory controllers, and power-management integrations. Proficient in SystemVerilog, SystemC, C/C++, Python, Perl and Ruby, he bridges architectural modeling and software validation—often enabling software teams via SystemC environments and co-simulation tools. Based in Apex, NC, he combines deep protocol and security block expertise (IPsec/MACsec, encryption/compression) with hands-on FPGA, emulation and silicon bring-up experience, making him effective from RTL to system validation. An unusual strength is his track record of building verification infrastructure that doubles as production-grade modeling for software and microcode development.
14 years of coding experience
13 years of employment as a software developer
Master's degree, Computer Science, Master's degree, Computer Science at North Carolina State UniversityBachelor's degree, Electrical, Electronics and Communications Engineering, Bachelor's degree, Electrical, Electronics and Communications Engineering at Birla Institute of Technology
Hindi
Github Skills (4)
react3
javascript3
textbook2
scheme2
Github contributions (5)
sanjeevs/golftracker
May 2022 - Nov 2024
Contributions:71 pushes, 1 branch in 2 years 5 months
Juniper/simple_reg_model
Aug 2017 - Aug 2018
Contributions:1 release, 43 commits, 34 pushes in 1 year 1 month
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