Sara Mahmoodi is a software engineer based in the San Francisco Bay Area with six years of experience focused on backend systems and CAD tooling for hardware design. As an R&D engineer and active GitHub contributor to the widely used Verilog-to-Routing (VTR) open-source project, she’s improved analytical placement, macro placement utilities, and robustness for high-utilization designs. She blends practical bug-fixing with thoughtful helper APIs and documentation refinements, showing attention to both correctness and maintainability. Comfortable working at the intersection of software and FPGA research, she brings a research-minded approach to production-quality code and a track record of improving complex placement flows.
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Backend Developer
Contributions:28 reviews, 272 commits, 35 PRs in 8 months
Contributions summary:Sara fixed bugs in the analytical placement component of the Verilog-to-Routing (VTR) flow, specifically addressing issues related to merging and growing regions within the cut spreader. They also implemented helper functions for placement within the `place_util.cpp` and header files, enhancing macro placement capabilities. Additionally, the user addressed format issues and provided improvements to comments and documentation in the relevant placement files. Furthermore, the user fixed initial placement problems with high utilization designs.
Contributions:6 PRs, 9 pushes, 7 branches in 4 months
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Sara Mahmoodi - Software Engineer at QuickLogic Corporation