Saranyu Chattopadhyay
Research Scholar at SRC Research Scholars Program
California City, California, United States
Summary
👤
Senior🎓
Top SchoolSaranyu Chattopadhyay is a research-focused electrical engineer and PhD candidate at Stanford with eight years of experience specializing in formal verification and hardware accelerator validation. As a Research Scholar in Stanford's Robust Systems Group and SRC Research Scholars Program, he developed A-QED methods that demonstrated 30x productivity improvements over conventional verification on real accelerator designs. His industry collaborations include a Qualcomm consultancy applying QED techniques under NDA and internships at Infineon and NVIDIA, reflecting a strong bridge between academic theory and commercial hardware practice. Past projects span hardware obfuscation, logic locking automation, and experimental work on spin-orbit torque devices, showing a blend of security, verification, and device-level expertise. He holds top academic credentials from Stanford and IIT Kharagpur and is actively scaling A-QED to tackle verification for large, loosely coupled accelerators. Unexpectedly, his background includes hands-on power-supply construction and fractal-lattice simulations, highlighting practical lab skills alongside formal methods.
8 years of coding experience
2 years of employment as a software developer
Bachelor’s Degree, Electronics and Electrical Communications Engineering, CGPA - 9.59, Bachelor’s Degree, Electronics and Electrical Communications Engineering, CGPA - 9.59 at Indian Institute of Technology, KharagpurDoctor of Philosophy - PhD, Electrical Engineering, CGPA - 3.99, Doctor of Philosophy - PhD, Electrical Engineering, CGPA - 3.99 at Stanford University
Github Skills (1)
testbench2
Programming languages (1)
Github contributions (5)
upscale-project/aqed-dac2020-results
Apr 2020 - Jun 2020
Contributions:37 commits in 1 month
upscale-project/aqed-decomp-FMCAD2021
Sep 2021 - Apr 2022
Contributions:16 commits, 1 push, 3 comments in 7 months
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