Schuyler Eldridge
Principal Engineer at SiFive
New York, New York, United States
Summary
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Rockstar🎓
Top SchoolSchuyler Eldridge is a Principal Engineer with 14 years of experience applying software engineering techniques—compilers, high-level and domain-specific languages—to accelerate hardware design and verification. Based in New York, he leads hardware compiler and IR work at SiFive, contributing to industry projects like Chisel, Rocket Chip, and FIRRTL and leveraging MLIR/CIRCT to modernize hardware toolchains. His background spans DARPA research and practical accelerator builds for RISC-V, including a PhD from Boston University and an open-source multilayer perceptron accelerator (DANA) from his dissertation. Notably, he blends deep compiler expertise with hands-on emulator and build-system improvements, often surfacing subtle developer ergonomics gains such as improved command-line tooling and IR-level optimizations.
14 years of coding experience
10 years of employment as a software developer
Doctor of Philosophy - PhD Computer Engineering, Doctor of Philosophy - PhD Computer Engineering at Boston University
Stackoverflow
2,784reputation
44kreached
46answers
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Github Skills (28)
hardware-designs10
verilog10
risc-v10
firrtl10
device-emulation10
intermediate-code10
scala10
compiler-design10
intermediate-language10
chisel10
rocket-chip10
emulation10
transformation10
c-language9
build-system9
Programming languages (20)
Github contributions (5)
chipsalliance/chisel
Oct 2016 - Jan 2023
Chisel: A Modern Hardware Design Language
Role in this project:
Back-end Developer
Back-end DeveloperContributions:836 reviews, 723 commits, 701 PRs in 6 years 4 months
Contributions summary:Schuyler primarily contributed to the `chisel` project, a modern hardware design language, by deprecating existing functionalities like the use of "Gender" and creating new types. These changes involve modifying core files and adding new classes for "Flow" conversion. The user also updated build dependencies, reconfigured website docs and added redirect feature.
rtlasicvhdllanguage-designeda
chipsalliance/firrtl
May 2017 - Mar 2022
Flexible Intermediate Representation for RTL
Role in this project:Backend Developer
Backend DeveloperContributions:165 reviews, 379 commits, 265 PRs in 4 years 10 months
Contributions summary:Schuyler primarily contributes to the development and maintenance of a Flexible Intermediate Representation for RTL. Their contributions include refactoring, fixing bugs, and implementing new features related to code generation and optimization within the FIRRTL framework. Key contributions include improving the handling of low-level IR constructs, the implementation of low-level IR const propagation, and modifications to name manipulation and memory representations. These changes demonstrate an understanding of compilers and hardware description languages.
representationtransformationintermediate-representationrtlcompiler
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