Scott Beamer
Associate Professor
California, United States
Summary
🤩
Rockstar🎓
Top SchoolScott Beamer is an associate professor and computer architect with 15 years of experience designing data-intensive systems that prioritize efficient data movement and communication. His work spans academia and open-source engineering, contributing to prominent projects like the RISC-V Spike simulator and the Rocket Chip generator, where he improved simulation fidelity, FPGA L2 cache support, and debugging tooling. He blends deep hardware understanding (memory interconnects, open-source hardware) with practical software and verification skills, having implemented and verified graph algorithms in the GAP benchmark suite and debugged Chisel tutorial tests. Based in California and trained at UC Berkeley under leading researchers, he brings a research-driven but applied approach to optimizing end-to-end system performance—often surfacing subtle correctness and compatibility fixes that improve toolchains and reproducibility.
15 years of coding experience
16 years of employment as a software developer
Ph.D., Computer Science, Ph.D., Computer Science at University of California, Berkeley
Github Skills (35)
graph-algorithms10
benchmark10
c-language10
risc-v10
benchmarking10
scala10
openmp10
sys10
chisel10
rt10
fpga10
embedded10
bfs-search10
rocket-chip10
cprogramming-language10
Programming languages (8)
Github contributions (5)
sbeamer/gapbs
Jun 2015 - Jun 2021
GAP Benchmark Suite
Role in this project:
Back-end Developer & Algorithm Implementer
Back-end Developer & Algorithm ImplementerContributions:10 releases, 1 review, 147 commits in 6 years 1 month
Contributions summary:Scott copied and adapted existing graph infrastructure code for a benchmark suite. They implemented and tested a graph converter as well as contributing code for connected components (CC), triangle counting (TC), breadth-first search (BFS), PageRank (PR), and single-source shortest path (SSSP) algorithms. This included integrating these algorithms and providing improvements like dynamic scheduling, as well as creating and implementing verifiers for these algorithms, to ensure correctness. The user's work significantly expanded the capabilities of the benchmark suite.
benchmarkingbenchmark-suitebfsbenchmarkgap
riscv-software-src/riscv-isa-sim
Sep 2013 - May 2020
Spike, a RISC-V ISA Simulator
Role in this project:Back-end Developer & Embedded Systems Engineer
Back-end Developer & Embedded Systems EngineerContributions:19 commits, 8 PRs, 3 pushes in 6 years 8 months
Contributions summary:Scott primarily focused on improving the RISC-V ISA simulator, Spike. Their contributions included fixing compiler bugs, adding support for register convention names, and cleaning up warnings. They also made significant changes to the commit logging functionality by printing privilege levels. Moreover, the user addressed compatibility issues and compile errors, demonstrating strong understanding of the codebase.
risc-visariscvriscv32simulator
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