Scott Nellenbach
Director, ASIC Development at Juniper Networks
Apex, North Carolina, United States
Summary
👤
Senior🎓
Top SchoolScott Nellenbach is a seasoned engineering leader with over a decade of experience driving ASIC, SoC, and networking silicon development for industry leaders like Juniper and Microsoft. He combines deep technical expertise in integrated circuit design, verification, architecture modeling, and cloud/HPC performance analysis with a proven ability to build and scale high-performing R&D teams and new site operations. At Microsoft he led SoC architecture and modeling to inform Azure HPC strategy, and at Juniper he delivered multiple generations of networking engines while open-sourcing tooling to improve register design workflows. He holds dual master’s degrees in Computer Science and Electrical Engineering, blending hardware rigor with software and infrastructure fluency. Known for turning complex silicon and system requirements into market-winning products, he also has a track record of cross-functional leadership that aligns engineering execution with business impact.
10 years of coding experience
11 years of employment as a software developer
Masters Computer Science, Masters Computer Science at North Carolina State UniversityMaster of Science Electrical Engineering, Master of Science Electrical Engineering at Rensselaer Polytechnic Institute
Github Skills (8)
registers10
uvm9
asic8
fpga8
eda8
systemverilog8
vlsi6
footprint1
Programming languages (2)
Github contributions (5)
Juniper/open-register-design-tool
Jun 2016 - Oct 2019
Contributions:18 releases, 16 commits, 11 PRs in 3 years 4 months
rtlsystemrdl-compilerasicsystemrdleda
sdnellen/open-register-design-tool
Oct 2019 - Oct 2021
Contributions:4 releases, 16 commits, 1 PR in 2 years
rtlasicsystemrdlcircuitseda
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