Scott Young
Instructor - Software Development at University of New Brunswick
St. John's, Newfoundland and Labrador, Canada
Summary
👤
Senior🎓
Top SchoolScott Young is a software development instructor and PhD candidate in computer science with 11 years of hands-on experience spanning language runtimes, garbage collection research, and FPGA CAD tooling. His academic work includes novel GC strategies that use page faults to distinguish hot and cold objects and JIT compiler research for Eclipse OpenJ9, while his open-source contributions improved Verilog-to-Routing parsing and AST loop handling for FPGA research. Based in St. John's, NL, he blends classroom instruction with active research and practical engineering, previously shipping backend systems and robotics experiments during industry and student research roles. Colleagues benefit from his ability to translate low-level systems insight into teachable concepts and production-ready tooling.
11 years of coding experience
2 years of employment as a software developer
Doctor of Philosophy - PhD, Computer Science, Doctor of Philosophy - PhD, Computer Science at University of New BrunswickBachelor of Science (B.Sc.), Computer Science, Bachelor of Science (B.Sc.), Computer Science at Memorial University of Newfoundland
English
Stackoverflow
1reputation
106reached
0answers
1question
Github Skills (13)
fpga10
synthesis10
verilog10
c-language10
cprogramming-language10
eda10
cad10
manipulation10
url-routing9
placement9
http6
redirect6
servlet6
Programming languages (5)
Github contributions (5)
verilog-to-routing/vtr-verilog-to-routing
Dec 2018 - May 2019
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer
Back-end DeveloperContributions:14 commits, 5 PRs, 7 comments in 5 months
Contributions summary:Scott primarily focused on enhancing the Verilog-to-Routing (VTR) flow, adding support for features like for loops and the `>>>` operator to the AST. They implemented modifications to the AST loop unrolling process, including functions for pre-processing, replacing, and resolving for loops. The user also added failing tests for unsupported loop behavior and updated the `spree.v` benchmark, demonstrating a strong focus on improving the Verilog parsing capabilities of the project.
vtrcadedaplacementsynthesis
Scott-Young-6746/vtr-verilog-to-routing
Oct 2018 - Apr 2022
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Contributions:26 pushes, 2 branches in 3 years 5 months
cadedasynthesisplacementrouting
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