Sean Huang
PHD Candidate
San Francisco Bay Area United States
Summary
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Top SchoolSean Huang is a PhD candidate at UC Berkeley specializing in generator-driven integrated circuit design, with deep expertise in digital clock generation and PLL/DCO architectures. Over eight years of experience includes designing a ring-oscillator DCO in 16nm FinFET, porting instances to Intel 22nm and SkyWater 130nm, and simulating a Bang-Bang PLL for local clock generation. He has interned twice at Apple developing proprietary mixed-signal modeling and layout-assist tools in Python, and built RTL for an OFDM CFO estimator using Chisel. Sean blends hands-on circuit design, automation (generator and spec-to-circuit flows), and verification across advanced process nodes, and is exploring extending DCO spec-driven methods to full PLL generation. Based in the Bay Area, he brings both academic rigor under Prof. Bora Nikolic and practical industry tooling experience to bridge specification and silicon.
7 years of coding experience
2 years of employment as a software developer
Bachelor of Science - BS, Electrical and Electronics Engineering, 3.79 GPA, Bachelor of Science - BS, Electrical and Electronics Engineering, 3.79 GPA at University of California, DavisDoctor of Philosophy - PhD, Integrated Circuit Design, Doctor of Philosophy - PhD, Integrated Circuit Design at UC Berkeley College of Engineering
English, Chinese, Spanish
Github Skills (29)
hammer9
wifi9
electrical-engineering9
camera9
bag8
hackage8
5g8
lte8
intermediate7
eagle6
agile6
circuit6
transformation5
modbus5
nimble5
Programming languages (5)
Github contributions (5)
ucberkeley-ee241b/ucberkeley-ee241b.github.io
Feb 2019 - Apr 2019
Contributions:26 commits, 19 pushes in 2 months
ucb-ee290c/fa18-modem
Oct 2018 - Dec 2018
LTE/WiFi/5G-NR SDR Transceiver
Contributions:189 commits, 177 pushes, 4 branches in 1 month
lte5gcamera5g-nrelectrical-engineering
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