Sébastien Van Cauwenberghe
FPGA Designer at NXP Semiconductors
Brussels, Brussels-Capital, Belgium
Summary
🤩
Rockstar🎓
Top SchoolSébastien Van Cauwenberghe is an experienced FPGA and embedded systems engineer with 13+ years building ASIC/FPGA designs, DSP implementations and embedded software for space, industrial and power-electronics applications. Currently at NXP and teaching FPGA design and DSP labs at ECAM Brussels, he blends hands-on silicon-level design with practical classroom mentoring. His career spans roles at Thales, Alstom and Space Applications Services where he delivered HDL design, FPGA validation with cocotb, embedded Linux and bare-metal ARM software. An active contributor to the SpinalHDL project, he added numeric and PDM cores and early floating-point support, demonstrating deep competence in hardware-oriented numerical methods and test automation. He also runs an independent development practice and has a track record of moving complex algorithms from specification to verified FPGA implementation. Based in Brussels with a Master in Electronics and Computer Sciences Engineering, he is as comfortable optimizing bitstreams as he is explaining them to students.
13 years of coding experience
10 years of employment as a software developer
Master, Electronics and Computer Sciences Engineering, Master, Electronics and Computer Sciences Engineering at Haute Ecole 'Léonard de Vinci', Bruxelles
English, Dutch, French
Github Skills (12)
rt10
fpga10
scala10
floating-point10
verilog10
numerics10
float3210
computation10
numerical10
numeric10
vhdl10
python8
Programming languages (8)
Github contributions (5)
SpinalHDL/SpinalHDL
Jul 2016 - Feb 2021
Scala based HDL
Role in this project:
Back-end Developer
Back-end DeveloperContributions:44 commits, 12 PRs, 5 pushes in 4 years 8 months
Contributions summary:Sébastien implemented several core functionalities within the SpinalHDL Scala-based HDL project. Their contributions include adding `min` and `max` functions and a `MaskByPriority` function to the `Utils.scala` file, enhancing the library's capabilities. Furthermore, they integrated a Pulse Density Modulation (PDM) core, incorporating Python testing scripts and Scala test configurations, showcasing proficiency in hardware design and testing methodologies. Additionally, the user added preliminary floating point support and converted between different floating point formats, highlighting a strong grasp of numerical computation within the HDL domain.
rtlhdlvhdlscalafpga
svancau/repeatercontroller
Dec 2012 - Apr 2013
Contributions:101 commits in 4 months
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