Seohee Kim is a Principal Engineer with 11 years of experience designing low-power SRAM and cache memory circuits for mobile and XR platforms, currently leading an international memory design group at Qualcomm in San Diego. She combines deep device-physics and fabrication expertise from a Ph.D. at UT Austin with hands-on CMOS circuit design and CAD/verification tool development, enabling chip-level power, redundancy and PPA optimization across diverse subsystems like DDR and multimedia. Her background spans both industry and academia—from PCM/PRAM development at Samsung to 2-D material and printed-electronics research—giving her a rare end-to-end perspective on memory from materials to system integration. Known for bridging research and production, she drives future production forecasting and cross-functional debug flows while mentoring teams on memory architecture and low-power strategies.
11 years of coding experience
16 years of employment as a software developer
Master of Science (M.S.) Electrical Engineering, Master of Science (M.S.) Electrical Engineering at Seoul National University
Doctor of Philosophy (Ph.D.) Electrical and Computer Engineering, Doctor of Philosophy (Ph.D.) Electrical and Computer Engineering at The University of Texas at Austin
Contributions:21 pushes, 1 branch in 2 years 3 months
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