Serina Tan is a computer architect with 11 years of experience specializing in software-hardware co-design for machine learning accelerators. Based in Cupertino, she currently contributes to the architecture of AWS custom ML chips (Inferentia/Trainium), bringing hands-on experience from earlier roles on the Neuron team and internships at Apple and AMD. Her background spans low-level graphics driver development, kernel debugging, and full-stack web tooling, enabling her to bridge silicon, firmware, and software stacks. She has a Master’s in Computer Engineering and a BASc from Waterloo, reflecting strong academic and practical foundations. Known for turning hardware constraints into software optimizations, she excels at improving inference performance through cross-layer collaboration. A quieter detail: her career path shows repeated returns to the same teams and projects, signaling deep domain focus and reliability.
11 years of coding experience
2 years of employment as a software developer
Master of Applied Science, Computer Engineering, Master of Applied Science, Computer Engineering at University of Toronto
Bachelor of Applied Science (BASc), Computer Engineering, Bachelor of Applied Science (BASc), Computer Engineering at University of Waterloo
A repository that compliments gpgpu-sim, providing automated regression scripts, simulation launching utilities and the code + arguments for simulations that complete in a reasonable amount of time on GPGPU-Sim.
Contributions:81 pushes, 1 branch, 1 tag in 6 months
regressionsimsimulationssimulationcompliments
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Serina Tan - Computer Architect at Amazon Web Services (AWS)