Seyed D

Toronto, Ontario, Canada

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Summary

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Seyed D is an FPGA and hardware/software co-design engineer with six years of experience applying EDA software design, machine learning, and deep learning to real-world hardware problems. He holds a Master's in Computer Science from the University of New Brunswick and a BS in Computer Hardware Engineering from the University of Tehran, blending academic rigor with practical CAD tool development. Seyed has contributed to the well-known open-source Verilog-to-Routing (VTR) project as a back-end developer and system architect, focusing on bug fixes that improved parser logic, netlist handling, and memory safety. His strengths lie in finding subtle logic errors and hard-to-detect memory issues across complex C/C++ codebases, making FPGA research tools more robust. Based in Toronto, he combines low-level hardware insight with data-driven techniques like regression analysis to optimize design flows. Colleagues describe him as a meticulous problem-solver who bridges academic research and production-quality EDA engineering.

6 years of coding experience

Master's degree, Computer Science, Master's degree, Computer Science at University of New Brunswick

Bachelor of Science - BS, Computer Hardware Engineering, Bachelor of Science - BS, Computer Hardware Engineering at University of Tehran

Github Skills (7)

memory-management10

debug10

c-language10

cprogramming-language10

verilog8

hdl8

yosys7

Programming languages (2)

C++SCSS

Github contributions (5)

verilog-to-routing/vtr-verilog-to-routing

Sep 2019 - Sep 2022

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Role in this project:

Back-end Developer & System Architect

Contributions:58 reviews, 566 commits, 125 PRs in 3 years

Contributions summary:Seyed primarily focused on Coverity bug fixes within the Verilog-to-Routing (VTR) project, specifically addressing issues in the ODIN_II and associated libraries. These fixes appear to involve resolving logic errors, correcting incorrect parameter usage, and mitigating potential memory leaks in the code. The user's contributions span various source files related to parsing, netlist creation, and memory management. They demonstrated expertise in identifying and correcting logic errors across multiple source files, contributing to a more stable and robust codebase.

vtrcadedaplacementsynthesis

sdamghan/vtr-verilog-to-routing

Oct 2019 - Sep 2022

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Contributions:71 PRs, 1084 pushes, 165 branches in 2 years 10 months

cadedasynthesisplacementrouting

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