Shaheer Sajid
Lahore, Punjab, Pakistan
Summary
👤
Senior🎓
Top SchoolShaheer Sajid is a Senior Hardware Engineer with 9 years of experience specializing in RTL-to-GDSII physical design, flow automation, and advanced-node implementation across Samsung 4 nm and TSMC 5 nm. As a founding member of DreamBig Semiconductor’s PD team, he built end-to-end implementation flows, automation frameworks, and methodology documentation that accelerated PPA closure and early signoff. His expertise spans floorplanning, power-grid architecture, CTS, and UPF domain setup, with practical innovations like via-ladder optimization and modular “Lego-like” PG integration that improved EM reliability and IR margins. He also led TSV-aware 3DIC automation and HBM interface work, and contributed an internal patent for ARM CMN interconnect optimization. Previously he led an RTL-to-GDSII tapeout of a 32-bit RISC-V MCU at NUST, delivering the full hardware–software ecosystem including FreeRTOS bring-up and an IEEE‑754 FPU. Based in Lahore, he combines deep hands-on physical design skills with a track record of methodology innovation and cross-functional mentorship.
9 years of coding experience
5 years of employment as a software developer
Master Electrical Engineering, Master Electrical Engineering at National University of Sciences and Technology, Pakistan
Github Skills (1)
fpu3
Programming languages (1)
Github contributions (5)
ShaheerSajid/PakFPU
Nov 2023 - Mar 2026
Fully paramterizable, IEEE-754 compliant FPU
Contributions:5 PRs, 57 pushes, 2 branches in 2 years 4 months
fpu
ShaheerSajid/OpenCV-Maze-Solving
Feb 2021 - Apr 2025
Contributions:18 pushes, 1 branch in 4 years 3 months
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