Shakti Chaganty
Physical Design Clocking Engineer at Apple
Austin, Texas, United States
Summary
👤
Senior🎓
Top SchoolShakti Chaganty is a Physical Design Clocking Engineer with 11 years of experience designing and implementing clock networks and driving block convergence on advanced nodes including 7nm and 10nm. Based in Austin, he has led complex clock-tree and partition closure efforts for Intel Xeon and graphics projects and now applies that expertise at Apple. He combines hands-on RTL-to-GDSII physical design flow proficiency with automation and custom clock solutions for large, multi-die floorplans, balancing power, performance, area, and reliability trade-offs. Comfortable with industry EDA toolchains (Synopsys, Cadence, Calibre) and scripting in Verilog/TCL, he brings both deep tool fluency and practical tape-in ownership experience. Notably, his background spans academia and industry—teaching embedded and microelectronic labs—giving him strong mentoring and systems-level insight beyond pure implementation.
11 years of coding experience
8 years of employment as a software developer
Jawaharlal Nehru Technological University HyderabadThe University of Utah
English, Hindi, TeluguGithub contributions (3)
shakti-chaganty/PhysicalDesignVLSI
Jul 2014 - May 2015
Contributions:15 commits, 7 pushes in 9 months
shakti-chaganty/Launch_Interceptor_Program
May 2015 - May 2015
Contributions:26 pushes, 1 branch in 1 day
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