Shee-jia Chin
R&D Manager at Akribis Systems
Singapore
Summary
👤
Senior🎓
Top SchoolShee-jia Chin is an R&D manager and full-stack embedded engineer with nine years of hands-on experience designing firmware, FPGA logic, and precision automation software from concept to production. Based in Singapore, she has led EtherCAT product development and driven system-wide engineering improvements at Akribis Systems, including unifying seven product FPGA codebases and cutting code size by roughly 65%. Her technical depth spans VHDL/Verilog, AXI interconnects, high-utilization FPGA timing closure, Ethernet PHY troubleshooting, and device driver/stack development for embedded TCP/IP. Shee-jia is pragmatic about engineering hygiene—championing Git adoption and unit testing (VUnit) to improve time-to-market and maintainability—while still contributing to schematic and hardware design when needed. Colleagues rely on her ability to bridge hardware, firmware, and application layers for micron-precision control systems, and she brings a rare blend of low-level timing expertise and product-focused systems thinking.
9 years of coding experience
9 years of employment as a software developer
Mathematics, Advanced Mathematics; Physics, Computer Science, Accounting, Economics, English, Mathematics, Advanced Mathematics; Physics, Computer Science, Accounting, Economics, English at Sayfol International School: MalaysiaMathematics B, Physics, English, Computer Science, Mathematics B, Physics, English, Computer Science at Sunway University CollegeBachelor of Electrical and Computer Systems Engineering (Hons), Bachelor of Electrical and Computer Systems Engineering (Hons) at Monash University
English, Chinese
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (49)
unit-testing10
verification10
vhdl10
asic10
vunit10
fpga10
testbench10
testing9
systemverilog9
lattice9
hardware-designs9
xilinx9
bash9
directories9
systemverilog-hdl9
Programming languages (3)
Github contributions (5)
cjchin/vunit
May 2017 - May 2023
VUnit is a unit testing framework for VHDL/SystemVerilog
Contributions:8 pushes, 2 branches in 6 years
testing-frameworkvhdltestingsystemverilogunit-testing-framework
cjchin/PoC
Feb 2018 - Feb 2018
Contributions:2 PRs, 14 pushes, 3 branches in 1 day
sciencefacultycore-libraryvlsicomputer-science
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