Shivam Aggarwal
Senior AI Compiler Engineer at Renesas Electronics
Singapore, Singapore
Summary
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Senior🎓
Top SchoolShivam Aggarwal is a Senior AI Compiler Engineer based in Singapore with nine years of experience bridging research and production for edge and automotive perception systems. He builds TVM-based Relay passes, ONNX quantization toolchains, and high-performance C++ kernels optimized for R-Car V4H DSP intrinsics and tensor cores, with deployments at Tier-1 autonomous-vehicle OEMs. A recent PhD from NUS focused on efficient model adaptation for Edge AI, he combines deep academic rigor with hands-on kernel prototyping—his R&D includes an 8-bit Flash Attention implementation for ViTs. His past internships at AMD and TCS produced practical advances in ultra-low-precision quantization and GAN-driven synthetic data for hand-gesture datasets. Comfortable across compiler passes, quantization research, and hardware-aware kernel tuning, he excels at turning cutting-edge ideas into deployable inference stacks.
9 years of coding experience
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, 8.69/10 (Top 10%), Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering, 8.69/10 (Top 10%) at Indraprastha Institute of Information Technology, DelhiDoctor of Philosophy - PhD, Computer Science, 4.58/5.0, Doctor of Philosophy - PhD, Computer Science, 4.58/5.0 at National University of Singapore
Github Skills (83)
binarization9
model-compression8
nvidia8
depth-estimation7
optimizer7
sdk7
transfer-learning7
tensorrt7
matching7
temporal-data7
pytorch-lightning7
ray6
pruning6
throughput6
deep-learning6
Programming languages (7)
Github contributions (5)
shivmgg/gem5-cache-partitioning
May 2019 - Dec 2019
Contributions:6 commits, 2 pushes in 7 months
shivmgg/osd-doc
May 2018 - Jun 2018
Open Soc Debug Documentation, including the specification
Contributions:2 PRs, 27 pushes, 6 branches in 1 month
formal-methodsspecificationedadecentralized-identitysoc
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