Shrujal Shah is a Silicon Design Verification Engineer with roughly a decade of experience building verification IPs and environments for storage and interconnect protocols such as SAS, SATA, ACE, AXI, and AHB. She has a strong hands-on background in SystemVerilog/Verilog, UVM/OVM methodologies, and common simulators (IUS, QuestaSim, VCS), having driven verification efforts at Google, Intel, Broadcom (via deputation), Cadence, and earlier startups. Her work spans active and passive VIP components, testplan and sequence development, and scripting automation in Perl and Shell to accelerate verification cycles. Comfortable bridging firmware-level C with hardware verification languages, she pairs protocol expertise with practical engineering to close coverage and integration gaps. Based in Ahmedabad, she also explores software stacks on GitHub (Node, Python, ML, Angular, React), reflecting a curiosity for full-stack and machine-learning tooling beyond core silicon verification. That blend of enterprise chip verification experience and broader software interest helps her navigate cross-domain problems and tooling integration.
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