Siddharth Sahay
Graduate Research Assistant
Pittsburgh, Pennsylvania, United States
Summary
👤
Senior🎓
Top SchoolSiddharth Sahay is a hardware-focused researcher and engineer pursuing graduate studies in Electrical and Computer Engineering at Carnegie Mellon University, specializing in FPGA systems, compilers, and embedded hardware-software co-design. He has hands-on experience building a Verilog compiler framework and code generator for a hardware services abstraction under Prof. James Hoe, adding features like profile-driven NoC port mapping and a Verilog DSL in Python. Prior internships include building a scalable SSL/TLS offloader in Erlang at India's National Informatics Centre and an analytical ETC report for NITI Aayog, reflecting a blend of systems programming and policy-minded analysis. With a B.Tech in Computer Science from Manipal Institute of Technology and roughly a decade of practical experience, he pairs deep low-level tooling skills with a knack for turning research prototypes into usable system components. An understated strength is his track record leading engineering work for CNC-driven business challenges, showing he can bridge technical design with real-world product and team outcomes.
10 years of coding experience
1 year of employment as a software developer
Bachelor of Technology (B.Tech.), Computer Science, Bachelor of Technology (B.Tech.), Computer Science at Manipal Institute of TechnologyDoctor of Philosophy - PhD, Electrical and Computer Engineering, Doctor of Philosophy - PhD, Electrical and Computer Engineering at Carnegie Mellon University
English, Hindi
Github Skills (25)
ieee9
trellis8
vivado8
fpga7
chromebox6
security6
speaker6
intrusion-detection5
alsa5
arch5
fedora4
audio4
blender3
upstream3
gem53
Programming languages (5)
Github contributions (5)
sidsahay/rubbish-lang
Feb 2019 - Jan 2020
Contributions:22 commits, 18 pushes, 5 branches in 10 months
sidsahay/neuerl
Jun 2017 - Jan 2020
Contributions:2 pushes, 1 branch in 2 years 7 months
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