Sisi Cao
TD Module Integration & Yield Engineer
Hillsboro, Oregon, United States
Summary
👤
Senior🎓
Top SchoolSisi Cao is a materials scientist and TD Module Integration & Yield Engineer at Intel with 11 years of experience bridging PhD-level research and cleanroom device fabrication. She specializes in materials characterization, synthesis of inorganic/organic nanostructures, and nano-/micro-fabrication of microelectronic and photonic devices, with a proven track record in data-driven yield improvement. Her background includes senior research work at Brewer Science and advanced degrees (MS, PhD) from Washington University in St. Louis, grounded in a bachelor’s from Hunan University. Sisi combines hands-on experimental skill with quantitative analysis to translate lab-scale innovations into manufacturable processes. Based in Hillsboro, Oregon, she brings both academic rigor and practical manufacturing experience to semiconductor integration challenges.
11 years of coding experience
Doctor of Philosophy (PhD), Materials Science, Doctor of Philosophy (PhD), Materials Science at Washington University in St. LouisBachelor's degree, Materials Science and Engineering, Bachelor's degree, Materials Science and Engineering at Hunan University
Chinese, English
Github Skills (8)
directmemory10
embedded10
c-programming10
linux-kernel10
sys10
dma10
device-driver9
driver9
Programming languages (1)
Github contributions (5)
bingbucao/linux
Jun 2022 - Feb 2025
Linux kernel source tree
Contributions:37 pushes, 2 branches in 2 years 8 months
kernellinux-distributionkernel-sourcelinuxlinux-kernel
intel/intel-ipu3-pipecfg
Dec 2019 - Jul 2021
Contributions:9 commits, 6 pushes, 1 branch in 1 year 7 months
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