Siyu Chen

Student at KTH Royal Institute of Technology

Stockholm, Sweden
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Summary

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Senior
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Top School
Siyu Chen is an ASIC developer and EIT Digital master student specializing in intelligent embedded systems, currently working at Ericsson in Kista with eight years of industry experience. He combines practical chip- and system-level design expertise with academic training from Southeast University and dual master's programs at University of Bologna and KTH. Comfortable in both hardware and software domains, Siyu contributes remotely to Verimake and focuses on bringing secure, optimized embedded solutions to telecommunications products. His background includes award-winning undergraduate performance and a cross-European education that gives him a strong grasp of international collaboration and multidisciplinary engineering. Colleagues describe him as a pragmatic problem-solver who translates complex specifications into reliable silicon and firmware.
code8 years of coding experience
bookBachelor of Engineering (B.Eng.), Electronic and Information Engineering, Outstanding Graduate Award, Bachelor of Engineering (B.Eng.), Electronic and Information Engineering, Outstanding Graduate Award at 东南大学成贤学院
bookKTH Royal Institute of Technology
bookMaster of Science, Embedded Systems, Master of Science, Embedded Systems at EIT Digital Alumni
bookLaurea Magistrale (Master of Science), Curriculum in Intelligent Embedded System, Laurea Magistrale (Master of Science), Curriculum in Intelligent Embedded System at Alma Mater Studiorum - Università di Bologna
languagesEnglish, Chinese
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Github Skills (29)

verilog10
fpga10
risc-v9
arduino9
hardware-acceleration8
plugin7
tcp6
debug6
serial-port5
raspberry5
esp82665
python5
udp5
raspberry-pi3
network3

Programming languages (5)

TypeScriptC++CVerilogPython

Github contributions (5)

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CSY-tvgo/YADAN-Docs

Aug 2021 - Feb 2023

RISC-V YADAN Core, YADAN SoC, YADAN Board's Documentation, designed for engineering education. // 鸭蛋的文档。
Contributions:2 reviews, 188 commits, 3 PRs in 1 year 5 months
arduinofpgahardware-accelerationrisc-vverilog
Contributions:21 commits, 17 pushes, 1 branch in 5 months
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Siyu Chen - Student at KTH Royal Institute of Technology