Sonal Santan - Senior Fellow at AMD

Sonal Santan

Senior Fellow at AMD

San Martin, California, United States

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Summary

👤

Senior

🎓

Top School

Sonal Santan is a Senior Fellow and architect specializing in runtime software stacks for hardware-accelerated platforms, with 12+ years focused on AIE, ACAP and FPGA systems spanning edge, client and data-center deployments. She led the open-source Xilinx RunTime (XRT) effort that underpins Alveo adaptable accelerator cards and contributed Python bindings and low-level API work on the widely used Xilinx/XRT GitHub repo. Her expertise bridges kernel and user space—Linux device drivers, PCIe, OpenCL runtimes, compiler/linker internals and virtualization—paired with hands-on HDL and assembly experience. At AMD and previously Xilinx she shaped product architectures, drove upstream open-source contributions, and holds 30+ US patents reflecting deep innovation in heterogeneous computing. Comfortable in C/C++/Python and familiar with LLVM, she pairs systems-level rigor with practical tooling that enables production ML and non-ML acceleration. Based in San Martin, CA, she combines decades of engineering depth with a knack for translating complex HW/SW interfaces into deployable runtime solutions.

12 years of coding experience

13 years of employment as a software developer

Indian Institute of Technology Kanpur

English, Hindi

Github Skills (4)

cprogramming-language10

c-language10

python10

memory-management9

Programming languages (4)

C++VHDLCPython

Github contributions (5)

Xilinx/XRT

Jun 2018 - Aug 2021

Run Time for AIE and FPGA based platforms

Role in this project:

Back-end Developer & Hardware Engineer

Contributions:9 releases, 271 reviews, 432 commits in 3 years 3 months

Contributions summary:Sonal contributed to the Xilinx Runtime (XRT) project, primarily focusing on low-level hardware interaction and API enhancements. They implemented the python bindings for XRT APIs to support PL kernels, including features for memory mapping and data transfers, demonstrating proficiency in integrating C++ and Python. The user updated the main test case to reflect the new PL APIs, and fixed bugs in the Python bindings.

vitisxilinxlinux-kernelxrtfpga

Xilinx/aiebu

Aug 2024 - Apr 2025

AIEBU

Contributions:40 reviews, 58 PRs, 34 pushes in 7 months

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