Summary
Srinivasan Ramesh is a Senior HPC Architect based in California with 11 years of experience designing performance-focused systems and tooling for GPU-accelerated supercomputing. Currently at NVIDIA, he develops performance modeling, analysis, and prediction tools for GPU-using HPC applications, building on a deep research background from a PhD program at the University of Oregon. His work bridges production and research—integrating and extending profiling stacks like TAU, Darshan, MVAPICH2, and OMPT to enable runtime introspection, monitoring, and autotuning of MPI/OpenMP/GPU workloads. He has a strong track record at national labs (Argonne, Brookhaven, LLNL) creating observability and monitoring services for distributed HPC microservices and ensemble applications. Known for turning research prototypes into practical tooling, he combines systems-level performance insight with hands-on experience optimizing scientific codes and runtime stacks.
11 years of coding experience
3 years of employment as a software developer
Doctor of Philosophy - PhD, Computer and Information Sciences, General, Doctor of Philosophy - PhD, Computer and Information Sciences, General at University of Oregon
BITS Pilani, Birla Institute of Technology and Science
English