Sripathi Muralitharan is a hardware engineer with a decade of experience designing digital systems and next-generation AI processors, currently based in Mountain View. He holds an MS in Electrical Engineering from the University of Washington (3.97 GPA) with a specialization in Computer Architecture and VLSI and a top-ranked B.Tech from NITK. His work spans academia and industry—from contributing to the open-source BlackParrot RISC-V multicore (notably D-cache design and cache miss tracking) to implementing lossless image compression in hardware at Facebook and building AI-processor hardware at a startup. Sripathi blends deep RTL and embedded systems expertise with system-level thinking, having improved cache coherence paths and integrated lock logic in multicore designs. Outside of engineering he is an active team player who plays basketball, piano, and enjoys social collaboration—traits that inform his pragmatic, multidisciplinary approach to processor and accelerator development.
10 years of coding experience
1 year of employment as a software developer
Master of Science - MS in Electrical Engineering, Electrical and Computer Engineering, 3.97/4.0, Master of Science - MS in Electrical Engineering, Electrical and Computer Engineering, 3.97/4.0 at University of Washington
Class 10 ICSE, Science, 97.2%, Class 10 ICSE, Science, 97.2% at New Horizon Public School
Class 12 CBSE, PCMC and English, 96.2%, Class 12 CBSE, PCMC and English, 96.2% at National Public School, Indiranagar
Bachelor of Technology (B.Tech.), Electronics and Communication Engineering, 9.55/10, Bachelor of Technology (B.Tech.), Electronics and Communication Engineering, 9.55/10 at National Institute of Technology Karnataka
A Linux-capable RISC-V multicore for and by the world
Role in this project:
Back-end Developer & Embedded Systems Engineer
Contributions:51 reviews, 47 commits, 14 PRs in 1 year 1 month
Contributions summary:Sripathi appears to be focused on developing and debugging the Black-Parrot RISC-V multicore. They contributed significantly to the design and implementation of the D-cache module. The user modified the code to include a cache miss tracker and integrated lock logic into the cache system to block processing of new dcache packets. They also made improvements to the LCE commands, Writebacks and Transfers.
A Linux-capable host multicore for and by the world
Contributions:34 pushes, 7 branches in 2 years 2 months
linuxmulticorehost
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Sripathi Muralitharan - Hardware Engineer at AI Startup