Srivatsa Yogendra
MTS Silicon Design Engineer at AMD
San Jose, California, United States
Summary
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Rockstar🎓
Top SchoolSrivatsa Yogendra is a seasoned silicon design and hardware verification engineer with eight years of experience building and validating SoC and embedded systems, currently at AMD after a multi-year tenure at SiFive. He holds an M.S. in Electrical and Computer Engineering from Portland State University with focused tracks in Embedded Systems Design and VLSI, and has hands-on expertise in SystemVerilog/Verilog verification, emulation on Veloce, AXI/AMBA protocols, RTOS and driver development. Srivatsa combines academic teaching experience on FPGA-based embedded systems with practical hardware engineering—from IMU/GPS/UWB integration to low-level assembly and microarchitecture work on MIPS and IA-32 concepts. He is an active contributor to the chipsalliance rocket-chip project, improving TileLink protocol implementations and adding verification cover points, reflecting a strong open-source pedigree in RISC-V tooling. Known for bridging pre-silicon verification and FPGA prototyping, he brings both deep protocol knowledge and pragmatic system-level perspective to complex silicon projects.
8 years of coding experience
7 years of employment as a software developer
Bachelor of Engineering (B.E.) Electrical Electronics and Communications Engineering, Bachelor of Engineering (B.E.) Electrical Electronics and Communications Engineering at Visvesvaraya Technological UniversityM.S Electrical and Computer Engineering, M.S Electrical and Computer Engineering at Portland State University
English
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (8)
risc-v10
chip810
rocket-chip10
chisel10
scala10
hdl9
rt9
hardware-designs9
Programming languages (3)
Github contributions (5)
chipsalliance/rocket-chip
Jul 2018 - Jan 2020
Rocket Chip Generator
Role in this project:
Back-end Developer & Hardware Engineer
Back-end Developer & Hardware EngineerContributions:1 review, 29 commits, 28 PRs in 1 year 5 months
Contributions summary:Srivatsa focused on implementing and refining TileLink protocol components within the Rocket Chip Generator. Their contributions include modifying the `Bundles.scala` file to define and align the messages related to the TileLink protocol and address issues like opcode and parameter passing. Further work involved adding methods to print the decode opcode and param values and improving the code by adding PMP cover points.
rtlriscvchipchiselscala
srivatsa611y/riscv-tools
Aug 2018 - Oct 2018
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
Contributions:5 pushes, 1 branch in 1 month
risc-visariscvgnusimulator
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