Stan Tian
Principal CAD Engineer at Astera Labs
Irvine, California, United States
Summary
👤
Senior🎓
Top SchoolStan Tian is a Principal CAD/EDA engineer with 11 years of experience building and scaling design flows for mixed-signal, RF and advanced-node digital ICs across semiconductor leaders. He has driven EDA methodology, tool evaluation, and vendor collaboration from chip bring-up to sub-20nm process qualification, most recently shaping CAD infrastructure at Astera Labs after senior roles at NXP and Lattice. Comfortable at the intersection of device physics and automation, Stan pairs hands-on analog/RF test and reliability research from USC with production EDA deployment and Insight-EDA development. Known for translating silicon-level issues into robust flows and scripting automation, he often bridges engineering teams and tool vendors to accelerate tapeout cycles. Based in Irvine, CA, he brings a pragmatic mix of academic rigor and field-proven problem solving to complex semiconductor design challenges.
11 years of coding experience
13 years of employment as a software developer
Bachelor of Science Electrical Engineering, Bachelor of Science Electrical Engineering at Michigan State University (MSU)Master of Science Electrical Engineering; Mixed Signal Circuit/RF Circuit Design, Master of Science Electrical Engineering; Mixed Signal Circuit/RF Circuit Design at University of Southern California (USC)
English, Chinese
Github Skills (2)
swift7
sqlite5
Programming languages (1)
Github contributions (5)
ping28198/TMTVision
Apr 2016 - Jun 2016
Contributions:46 commits, 31 pushes in 2 months
Stanley-Tian/ApartmentReality
Jun 2016 - Aug 2016
Contributions:43 pushes, 4 branches in 1 month
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