Stefan Wallentowitz
Vice Chair Board Of Directors at Munich University of Applied Sciences
Bavaria, Germany
Summary
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Rockstar🎓
Top SchoolStefan Wallentowitz is a seasoned computer architect and open-source hardware advocate with 15 years of experience bridging academia, industry and standards bodies from Bavaria, Germany. As Vice Chair of the RISC-V International Board and a professor focused on computer architecture and hardware security, he blends strategic leadership with hands-on engineering. His open-source contributions span core CPU work—improving caches, multicore support and debug infrastructure for OpenRISC and RISC-V cores—to test automation and build tooling for cocotb and FuseSoC, demonstrating deep RTL, simulation and verification expertise. He has steered practical integrations like UART-based memory access for lowRISC FPGA demos and improved documentation and tooling that make small CPU cores more accessible to engineers. With a PhD from TUM and an uncommon combination of academic teaching, standards governance and low-level silicon engineering, he is adept at turning complex microarchitectural ideas into usable, verifiable implementations.
15 years of coding experience
6 years of employment as a software developer
Doctor of Philosophy - PhD, Electrical and Electronics Engineering, Doctor of Philosophy - PhD, Electrical and Electronics Engineering at Technical University MunichMaster of Business Administration (MBA), Economics and Business Administration, Dipl.-Wirt.-Ing., Master of Business Administration (MBA), Economics and Business Administration, Dipl.-Wirt.-Ing. at RWTH Aachen University
English, German, Italian
Stackoverflow
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Github Skills (26)
uart10
hardware-designs10
verilog10
systemverilog10
python10
sphinx10
testing10
risc-v10
verification10
hardware10
vhdl10
verilator10
sys10
build-automation10
fpga10
Programming languages (26)
Github contributions (5)
openrisc/mor1kx
Sep 2013 - Apr 2017
mor1kx - an OpenRISC 1000 processor IP core
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:60 commits, 7 PRs, 11 pushes in 3 years 7 months
Contributions summary:Stefan primarily contributed to the OpenRISC 1000 processor IP core, focusing on optimizing and enhancing the data cache (DCache) and instruction cache (ICache) functionality. Their work involved implementing coherency through the snoop port, supporting multiple cache ways, and fixing bugs related to Least Recently Used (LRU) unit and store buffer mechanisms. They also added a core identifier and multicore support. Furthermore, they refactored the code by renaming variables, addressing potential issues related to atomic operations, and refining the execution traceport.
openriscverilog
olofk/fusesoc
Mar 2016 - Feb 2021
Package manager and build abstraction tool for FPGA/ASIC development
Role in this project:Backend Engineer
Backend EngineerContributions:15 commits, 28 PRs, 14 pushes in 4 years 11 months
Contributions summary:Stefan primarily contributed to the FuseSoC project by implementing and refactoring core functionalities related to the build process. They focused on improving the handling of configuration files, specifically addressing warnings and hierarchical naming schemes. The user also addressed path sanitization issues, introduced command-line argument forwarding, and added a Vivado backend, which expands the project's compatibility with other FPGA/ASIC development tools.
asicpythonvhdledapackage-manager
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