RTL, Cmodel, and testbench for NVDLA
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Backend Developer Contributions:14 commits, 3 pushes, 21 comments in 4 months
Contributions summary:Stephen's commits primarily involve modifying and refactoring SystemVerilog code within the NVDLA hardware repository. They are removing legacy code, specifically the GetArgValPLI function, and replacing it with more modern alternatives. The user is also making significant changes to the testbench, particularly in the FIFO modules (id_fifo, raddr_fifo, memresp_fifo, wdata_fifo), including adding support for AXI burst lengths and updating memory access patterns. These updates suggest a focus on improving code maintainability and functionality within the hardware verification environment.
rtltestbenchnvdla
Contributions:1 commit in 1 day
documentation-generatornvdla