Steve Hughes
Sr. Application Analyst
Austin, Texas, United States
Summary
🤩
Rockstar🎓
Top SchoolSteve Hughes is a senior application analyst and CRM specialist with over 6 years of focused experience aligning Salesforce-driven systems to sales, marketing, and operations goals across companies like Q2, Silicon Labs, Planview, and OpenClassrooms. He combines deep hands-on administration and integration experience—managing DocuSign, Marketo, HubSpot, Conga, LeanData and other ecosystems—with a track record of delivering scalable automations that improve data quality, forecasting, and revenue operations. Steve has led complex instance migrations and merges, implemented CPQ and renewal tracking that supported multi-million-dollar forecasts, and served as a trusted partner to sales and marketing leadership. Beyond CRM, he contributes to open-source RISC-V verification and core projects, demonstrating low-level engineering chops through SystemVerilog and simulation tooling enhancements. Based in Austin, he brings a pragmatic blend of technical problem-solving, process design, and user-focused training that turns strategic vision into operational outcomes. Those who work with him note his ability to translate stakeholder pain points into durable, auditable solutions that scale.
6 years of coding experience
13 years of employment as a software developer
CEGEP - John Abbott CollegeBachelor of Science, Kinesiology, Bachelor of Science, Kinesiology at University of New BrunswickAssociate Bachelor, Database Development and Design, Associate Bachelor, Database Development and Design at Technical SchoolBHS
Github Skills (23)
debugging10
debug10
gnu-make10
systemverilog10
architecture10
computer-architecture10
risc-v10
makefile10
sys10
instruction-set10
embedded10
architectures10
test-automation10
c-language9
pipelining9
Programming languages (4)
Github contributions (5)
openhwgroup/core-v-verif
Jul 2020 - Dec 2021
Functional verification project for the CORE-V family of RISC-V cores.
Role in this project:
Back-end Developer
Back-end DeveloperContributions:269 reviews, 819 commits, 513 PRs in 1 year 5 months
Contributions summary:Steve Richmond's contributions focus on enhancing the verification project for the CORE-V family of RISC-V cores. He primarily worked on improving the simulation makefiles, including updating the build system and integrating the Imperas ISS. His contributions included adding new test configurations, managing and incorporating code coverage, and addressing critical bugs in the debug process with regards to the handling of Instruction Bus Faults and the core execution cycle.
risc-vsystemverilogriscverificationcores
openhwgroup/cv32e40p
Aug 2020 - May 2021
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Role in this project:Embedded Systems Engineer / IoT Developer
Embedded Systems Engineer / IoT DeveloperContributions:2 reviews, 16 commits, 12 PRs in 8 months
Contributions summary:Steve primarily focused on enhancements to the instruction tracing capabilities of the CV32E40P core. They refactored the tracer module to improve its resilience to pipeline stalls and implemented a state-machine style design. Furthermore, they added functionality to handle ebreak instructions and signal the compressed instructions to the functional coverage. The work involved significant modifications to the SystemVerilog code related to instruction tracing and core behavior.
risc-vcpupulpuvmriscv
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