Steven Yang
ASIC Design Engineer at Apple
San Jose, California, United States
Summary
👤
Senior🎓
Top SchoolSteven Yang is a seasoned ASIC Design Engineer with 25+ years driving complex ASIC and SoC projects across networking, home networking, and data-center Smart NIC domains, now contributing at Apple. He blends deep RTL and microarchitecture expertise with hands-on synthesis, static timing closure, FPGA emulation and post-silicon validation, having closed timing at 1.4GHz for 8x50Gbps SERDES integrations. His background spans Ethernet/TCP-IP, MoCA, UWB, PCIe, Interlaken and mixed-signal integration, and he has led architecture and top-level integration from specification through silicon at Broadcom, Marvell, Cisco and others. Steven is also an inventor with more than ten patents filed/issued and a track record of translating system-level requirements into robust, low-power silicon. Based in San Jose, he combines deep lab debugging experience (logic analyzers, scopes, spectrum analyzers) with team and project leadership across both startup and hyperscaler environments. Notably, his career covers both legacy interfaces (Token Ring, ISA) and cutting-edge multi-hundred-Gbps SERDES, showing rare breadth across generations of chip design.
14 years of coding experience
29 years of employment as a software developer
The University of Maryland, College Park
Github Skills (200)
go-packages10
server-name10
alias10
unsupervised-learning10
configuration-file10
tcp10
anomaly-detection9
proxy9
http9
openvino9
yeoman9
yeoman-generator9
scaffold9
closure9
plovr9
Programming languages (19)
Github contributions (5)
yangchenyun/learning-sicp
Aug 2012 - Feb 2017
Contributions:108 commits, 3 pushes in 4 years 6 months
yangchenyun/history_of_languages
Feb 2014 - Feb 2014
Contributions:86 commits in 5 days
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