Stevo Bailey
Senior ASIC Design Engineer at Amazon Lab126
San Francisco Bay Area United States
Summary
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Rockstar🎓
Top SchoolStevo Bailey is a Senior ASIC Design Engineer based in the San Francisco Bay Area with 11 years of experience building robust, power-efficient processors and custom silicon from research to production. He holds BS degrees in Engineering Science and Physics from UVA, an MS from UC Berkeley, and is finishing a PhD at Berkeley focused on rapid ASIC design methodologies, blending deep academic research with industry practice. His career spans roles at Amazon Lab126 and Mojo Vision, with internships at JPL and NVIDIA, and hands-on contributions to Chisel-based open-source training materials where he implemented low-level hardware primitives like FIFOs and MUXes. Known for bridging fault-tolerant nanoelectronic research and practical ASIC flow improvements, he brings both circuit-level insight and generator-driven hardware design expertise. Outside work he keeps a disciplined, performance-oriented routine—piano, regular runs, and gym sessions—that mirrors his approach to engineering.
11 years of coding experience
10 years of employment as a software developer
Doctor of Philosophy (PhD), Electrical Engineering and Computer Science, Doctor of Philosophy (PhD), Electrical Engineering and Computer Science at University of California, BerkeleyBachelor of Science (B.S.), Engineering Science, Bachelor of Science (B.S.), Engineering Science at University of Virginia
Stackoverflow
11reputation
146reached
2answers
0questions
Github Skills (9)
chisel10
digital-design10
digital-logic10
logic10
verilog9
scala8
risc-v6
sbt6
sbt-assembly6
Programming languages (10)
Github contributions (5)
freechipsproject/chisel-bootcamp
Jul 2017 - Mar 2018
Generator Bootcamp Material: Learn Chisel the Right Way
Role in this project:
Backend Developer
Backend DeveloperContributions:59 commits, 8 PRs, 37 pushes in 7 months
Contributions summary:The user, "stevo", is primarily focused on developing hardware descriptions using the Chisel hardware construction language within the context of a Generator Bootcamp. The user's work centers around building combinational and sequential logic circuits by modifying a notebook file within the repository. The user implemented multiple Chisel modules including a FIFO, MUX, and other low-level blocks.
chiselhardwarevhdl
stevobailey/website
Mar 2015 - Oct 2020
Contributions:5 pushes in 5 years 7 months
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