Summary
Sukanta Dey is an EDA Tools Software Engineer with a decade of experience building RTL-to-GDSII flows, physical-design tooling, and security-aware EDA solutions for advanced process nodes. Currently at Intel's AMS PESG extraction team, he focuses on pathfinding and tool/flow/methodology development for 18A/20A nodes, leveraging Cadence and OpenRoad toolchains. A Ph.D. from IIT Guwahati in Machine Learning for EDA, he has led funded research at the University of Florida that automated RTL-to-layout flows and produced datasets and AI frameworks for power side-channel analysis. He combines deep software engineering (C/C++, Python, parallel APIs) with VLSI domain expertise in IR/EM sign-off, placement/routing, and analog extraction, and has a track record of turning research prototypes into practical sign-off methodologies. Notably, he has experience mentoring teams and delivering pre-silicon security roadmaps and tools supported by industry partners like Synopsys and Ansys.
10 years of coding experience
7 years of employment as a software developer
Senior Secondary School, Science, Senior Secondary School, Science at Maharishi Vidya Mandir Senior Secondary School
M.Tech. + Ph.D., Computer Science and Engineering, Machine Learning for EDA, M.Tech. + Ph.D., Computer Science and Engineering, Machine Learning for EDA at Indian Institute of Technology, Guwahati
High School, General, High School, General at Kamakhya Vidyalaya High School, Maligaon, Guwahati
Bachelor of Engineering (B.E.), Electronics and Telecommunication Engineering, Bachelor of Engineering (B.E.), Electronics and Telecommunication Engineering at Assam Engineering College, (A.E.C)
Hindi, Assamese, Bengali, English