Suraj Vellengar
Principal Engineer at SiFive
Austin, Texas Metropolitan Area United States
Summary
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Rockstar🎓
Top SchoolSuraj Vellengar is a Principal Engineer based in Austin with over 6 years of focused experience in CPU verification and subsystem validation, specializing in RISC-V and ARM fetch, MMU, and advanced interrupt architectures. He brings deep hands-on expertise in UVM/SystemVerilog/UVC development, ASIC-to-FPGA porting, and peripheral verification across AXI, AHB, I2C and DDR interfaces. At SiFive he progressed from Staff to Principal Engineer, demonstrating both technical leadership and a track record of delivering complex block- and top-level verification for CPU designs. Known for mentoring teams and driving quality and schedule discipline, he blends low-level architectural understanding with practical validation strategies. A detail-oriented engineer, he pairs protocol-level verification rigor with system-level integration experience that shortens bring-up cycles and improves silicon readiness.
6 years of coding experience
10 years of employment as a software developer
Bachelor’s Degree Electronincs, Bachelor’s Degree Electronincs at Sanjeevani Education Societys College of EngineeringJijamatha education societies sadhavi parathishudahji English medium schoolPG Diploma VLSI, PG Diploma VLSI at CDAC
Github Skills (9)
circuit9
scala8
chisel7
llvm7
rocket-chip7
unikernel7
bazel6
rocket6
compiler4
Programming languages (2)
Github contributions (5)
surajvellengar/rocket-chip
Feb 2020 - Feb 2020
Rocket Chip Generator
Contributions:1 push, 1 branch in 8 days
doschiprocketrocket-chipchip-generator
surajvellengar/riscv-isa-sim
Jul 2020 - Jul 2020
Spike, a RISC-V ISA Simulator
Contributions:1 branch in 1 day
risc-visariscvsimulatorrisc
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