Svyatoslav Smirnov
Senior RTL Hardware Engineer at Syntacore
Saint Petersburg, Saint Petersburg, Russia
Summary
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Senior🎓
Top SchoolSvyatoslav Smirnov is a Senior RTL Hardware Engineer with 9 years of experience designing and verifying ASIC and FPGA logic, currently leading RTL development at Syntacore. He specializes in scalable, parameterized RTL architectures, frequency and area optimization, timing-driven design (SDC), and automation of flows with TCL/Python/Bash integrated into Jenkins CI. His verification skill set covers OOP-based constrained-random UVM, SVA/SVC assertions, coverage analysis and basic formal verification using Cadence Jasper. Previously as an FPGA engineer he delivered complex network and transceiver solutions (Arria/Stratix/Cyclone families), protocol stacks and ADC/DAC integrations, often bridging hardware with MATLAB-based debugging and GUIs. Comfortable across the full RTL toolchain (VCS, ModelSim, Genus, Quartus) and versioning systems (Git, SVN, GitLab), he combines hands-on implementation with pipeline automation to accelerate delivery. Colleagues rely on him for pragmatic, reusable hardware abstractions that hide board differences and simplify scaling across product variants.
9 years of coding experience
8 years of employment as a software developer
Saint Petersburg State Electrotechnical University "LETI"
Russian, English
Github Skills (58)
packed10
rendering9
xamarin-android9
webgl9
typescript9
android-sdk9
csharp9
3d9
webvr9
xamarin-forms9
engine9
joystick9
opengl-es8
rendering-engine8
scientific-visualization8
Programming languages (2)
Github contributions (5)
shults-s/SmtuSchedule
Feb 2019 - Nov 2020
Contributions:11 releases, 466 commits, 13 PRs in 1 year 9 months
shults-s/shults-s.github.io
Jun 2019 - Jun 2019
Contributions:15 pushes, 1 branch in 1 day
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