Tao Liu
Senior Software Engineer at Google
San Francisco Bay Area United States
Summary
🤩
Rockstar🎓
Top SchoolTao Liu is a Senior Software Engineer based in the San Francisco Bay Area with eight years in industry and deep experience in wireless networking, sensors, and IoT-focused tooling. At Google (and previously Fluke Networks) he builds robust, production-grade systems while contributing to low-level verification and embedded work—evidenced by notable open-source contributions to RISC-V projects like riscv-dv and the Ibex core where he improved instruction generation, encoding fixes, and integration for DV testing. Proficient in C/C++ and exploring Haskell, he combines firmware and backend skills to deliver WiFi monitoring and InfoSec applications that bridge hardware and software. He holds advanced degrees including an MSc in Internet and Multimedia Engineering and a PhD in Computer Science, bringing research-grade rigor to practical engineering challenges.
8 years of coding experience
7 years of employment as a software developer
B.E, Power System and Its Automation, B.E, Power System and Its Automation at Wuhan UniversityM.Sc, Internet and Multimedia Engineering, M.Sc, Internet and Multimedia Engineering at London South Bank UniversityDoctor of Philosophy (PhD), Computer Science, Doctor of Philosophy (PhD), Computer Science at University of California, Merced
English, Chinese
Github Skills (12)
risc-v10
embedded10
assembly10
systemverilog10
sys10
hardware10
assembler10
test-automation10
uvm9
verilog8
c174
c114
Programming languages (4)
Github contributions (5)
chipsalliance/riscv-dv
Jan 2019 - Mar 2021
Random instruction generator for RISC-V processor verification
Role in this project:
Backend Developer & Test Automation Engineer
Backend Developer & Test Automation EngineerContributions:10 reviews, 383 commits, 700 PRs in 2 years 2 months
Contributions summary:Tao primarily contributed to improving the stability and correctness of the RISC-V instruction generator. The commits focus on fixing issues related to instruction encoding, branch offsets, and incorrect setting of registers. The user also added support for experimental features and new test cases to enhance the generation process.
risc-vriscinstructionverification
lowRISC/ibex
May 2019 - Mar 2020
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:48 commits, 94 PRs, 46 pushes in 9 months
Contributions summary:Tao contributed to the `lowrisc/ibex` repository, a 32-bit RISC-V CPU core, by integrating and updating the RISC-V DV (Design Verification) code. This included adding vendor configurations, patches, and adapting scripts to incorporate RISC-V DV testing. Furthermore, the user made modifications to the assembly program generation, core settings, and test lists to align with the RISC-V DV integration and overall verification process. These changes improve the testing and verification of the Ibex core.
risc-vcpuzeroibex32-bit
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