Tejash Shah is a product-minded AI software leader with 7 years in AI/ML platform and a long engineering pedigree spanning Qualcomm, AMD and NVIDIA. He has driven compiler and runtime integrations for edge and accelerator hardware—building Snapdragon Adreno/NPU support in TVM and contributing 3D batch-norm support to AMD's MIOpen—bridging low-level kernel work with product roadmaps. At OctoAI/NVIDIA he led cross-geo teams to expand ML compiler support for customers like Samsung and ByteDance, and he mentors engineers on kernel-level optimization for transformer workloads. He combines hands-on GPU/HIP/OpenCL performance tuning with strategic partner engagement and a knack for translating hardware nuances into developer-friendly tooling. Based in San Diego, he pairs a master’s in CS with deep domain experience in inference and training stacks, often surfacing pragmatic trade-offs that keep both performance and ecosystem adoption aligned.
7 years of coding experience
18 years of employment as a software developer
Master's Degree Computer Science, Master's Degree Computer Science at The University of Texas at Dallas
Bachelor's Degree Computer Science, Bachelor's Degree Computer Science at Gujarat University
Contributions:3 reviews, 98 commits, 8 PRs in 1 year 11 months
Contributions summary:Tejash focused on adding support for 3D batch normalization to AMD's Machine Intelligence Library (MIOPEN). Their work included implementing the necessary driver functionalities for 3D batchnorm, modifying existing API calls for 3D tensor descriptors, and adding unit tests for the new 3D batchnorm functionalities. The user's contributions were focused on adding support for various 3D tensor processing in the batch normalization APIs.
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