Summary
Teng Wang is an engineering manager and seasoned hardware designer with two decades of experience in digital and ASIC design, currently leading circuit teams at Apple in Seattle. He has a proven track record building characterization, QA and frontend modeling flows at Qualcomm that became daily execution tools and led distributed teams across the US and India. Technically fluent in VHDL/Verilog, Synopsys, Cadence and mixed-signal verification, he’s delivered high-speed timing loops, Sigma-Delta A/D modules and VLIW processor blocks from tapeout to production. Teng pairs deep hands-on RTL and CAD tool expertise with management of cross-cultural engineering teams, and has a PhD-level electrical engineering background that informs his methodical, measurement-driven approach. A wry sense of humor on GitHub (“Chief BaiLan Officer”) hints at an approachable leader who values pragmatic engineering and team culture.
6 years of coding experience
15 years of employment as a software developer
Bachelor, Electrical Engineering, Bachelor, Electrical Engineering at University of Science and Technology of China
PhD, ECE, PhD, ECE at University of Massachusetts Amherst
Master, ASIC design, Master, ASIC design at Chinese Academy of Sciences