Teng Xingning
Principal Design Service Engineer at Cadence Design Systems
Shanghai, Shanghai, China
Summary
👤
Senior🎓
Top SchoolTeng Xingning is a Principal Design Service Engineer with over 15 years of SoC physical design expertise, specializing in timing, SI, power/EM/IR, DFM closure and low-power CPF-based implementations across advanced nodes (65nm down to 28nm and below). He has led giga-scale chip planning and hierarchical flows for mobile baseband SoCs and high-speed Cortex-A implementations, contributing to multiple successful tapeouts including quad-core 28nm designs running near 1.2 GHz. At Cadence and earlier at VeriSilicon and ACE Semiconductor, Teng combined hands-on implementation, methodology development and customer-facing support for synthesis, P&R, signoff and ECO flows for major customers like TI, NXP and IBM. He is skilled at orchestrating cross-functional teams, defining timing budgets and driving project schedules for complex, low-power and high-performance chips. Uncommonly for backend specialists, Teng also lists an interest in speech signal processing on GitHub, hinting at broader signal-level curiosity beyond physical design. Based in Shanghai, he brings both deep toolchain knowledge and proven tapeout leadership to challenging semiconductor programs.
9 years of coding experience
6 years of employment as a software developer
Master's degree, Microprocessor Systems and Instrumentation, A, Master's degree, Microprocessor Systems and Instrumentation, A at Zhejiang University
Github Skills (16)
gmm10
mls9
proxy8
bypass8
vscode-plugin8
signal-processing8
vpn8
speech8
goagent7
pitch7
speech-recognition6
wpe6
annotations4
vscode4
vscode-extension3
Programming languages (2)
Github contributions (5)
helianvine/fdndlp
Aug 2018 - May 2019
A speech dereverberation algorithm, also called wpe
Contributions:5 commits, 3 PRs, 18 pushes in 9 months
wpedereverberationmlsspeech-recognitiongmm
helianvine/helianvine.github.io
Oct 2017 - Oct 2017
Contributions:18 pushes, 2 branches in 11 days
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