Theo Kluter
Professor Electrical And Communication Engineering
Neuchâtel, Neuchâtel, Switzerland
Summary
🤩
Rockstar🎓
Top SchoolTheo Kluter is a Professor of Electrical and Communication Engineering with over a decade of academic experience and a PhD from EPFL, combining deep research expertise with long-standing industry practice in FPGA design. He teaches digital logic and analog technology at Bern University of Applied Sciences and EPFL, mentoring the next generation of engineers with a pragmatic, mistake-avoiding approach. His early industry work as an FPGA design engineer informs hands-on curriculum and practical hardware-software integration skills. An active contributor to the popular Logisim-evolution project, he has improved HDL code generation and FPGA IO support, demonstrating attention to tooling accuracy and user-friendly hardware simulation. Based in Neuchâtel, Switzerland, Theo blends rigorous academic training with concrete engineering improvements that make complex digital design more accessible.
10 years of coding experience
6 years of employment as a software developer
Master, Electrical Engineering, Master, Electrical Engineering at University of TwenteIng., Electrical Engineering, Ing., Electrical Engineering at HanzePhD, Computer and Communication Sciences, PhD, Computer and Communication Sciences at EPFL
Dutch, English, German, French
Github Skills (11)
fpga10
circuit10
javas10
debug10
digital-design10
java10
pg10
digital-logic10
logic10
develop8
testing8
Programming languages (4)
Github contributions (5)
logisim-evolution/logisim-evolution
Sep 2015 - Jan 2023
Digital logic design tool and simulator
Role in this project:
Back-end Developer & Electrical Engineer
Back-end Developer & Electrical EngineerContributions:21 releases, 546 reviews, 1695 commits in 7 years 5 months
Contributions summary:Theo primarily worked on improving the Logisim-evolution digital logic design tool by fixing bugs and enhancing the generation of hardware description language (HDL) code. They addressed issues related to LED array mapping and exceptions. The user introduced features to rotate and integrate various FPGA IO components like 7-segment displays, dip switches, and LED arrays. These changes show a focus on improving the accuracy and user-friendliness of HDL code generation for various FPGA components.
digital-circuitsvhdlcircuitssimulationdigital-logic
BFH-ktt1/logisim-evolution
Aug 2021 - Aug 2022
Digital logic designer and simulator
Contributions:61 commits, 880 pushes, 303 branches in 1 year
circuitsdesignersimulationsimulatordigital-logic
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.