Thomas Chau
Senior Staff Engineer, NPU Hardware Architecture at Intel Corporation
Mountain View, California, United States
Summary
👤
Senior🎓
Top SchoolThomas Chau is a Senior Staff Engineer specializing in NPU hardware architecture with 12 years bridging industry and academia, currently architecting integrated NPUs for Core Ultra processors in Mountain View. He holds a PhD from Imperial College London on a full scholarship, is a Chartered Engineer, and has authored over 30 publications and patents at the intersection of ML and hardware. His work spans startups to hyperscalers — from taping out MLPerf-capable silicon at Neubla to driving mobile TPU design at Google and hardware-aware model optimization at Samsung. Thomas blends deep microarchitectural design, ISA definition, and hardware/software co-design with practical experience in performance modeling, compiler collaboration, and low-power mobile constraints. A rare combination of rigorous research pedigree and hands-on chip delivery, he repeatedly translates emerging ML workloads into efficient, programmable silicon.
12 years of coding experience
7 years of employment as a software developer
Doctor of Philosophy (PhD), Computing, Doctor of Philosophy (PhD), Computing at Imperial College LondonThe Chinese University of Hong Kong (CUHK)
English, Chinese, Chinese, Korean
Github Skills (2)
building-blocks3
dataflow1
Programming languages (1)
Github contributions (5)
thomasccp/thomasccp.github.io
Jan 2015 - Jul 2024
Contributions:145 pushes in 9 years 7 months
custom-computing-ic/smcgen
Feb 2014 - Feb 2015
Contributions:224 commits, 2 pushes in 1 year
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