Thomas Preußer
Fellow at AMD
Dresden, Saxony, Germany
Summary
🤩
Rockstar🎓
Top SchoolThomas Preußer is a Principal Research Engineer with 14 years of expertise in digital design, embedded systems and massively parallel FPGA computation, currently driving research at AMD after roles at Xilinx and Accemic. He bridges low-level RTL accelerator design and high-level software integration, routinely exposing FPGA functionality through C++/Java APIs and AXI-Lite interfaces. His work spans academia and industry—from a Marie-Curie fellowship and ETH Zürich postdoc to leading R&D teams building line-rate FPGA solutions for processor trace analysis. Notably, he has contributed hardware-verified dataflow components to the popular Xilinx/finn project, reflecting deep verification and hardware-software co-design skills. Adept at heterogeneous platforms like Zynq, he combines rigorous academic training (Dr.-Ing., magna cum laude) with practical systems engineering to deliver high-throughput, production-ready accelerators.
15 years of coding experience
16 years of employment as a software developer
Exchange Student Computer Engineering, Exchange Student Computer Engineering at The University of Texas at AustinDoktoringenieur (Dr.-Ing.) Computer Engineering, Doktoringenieur (Dr.-Ing.) Computer Engineering at Technische Universität Dresden
German, English, Russian
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (18)
hardware-designs10
dataflow-programming10
dataflow10
systemverilog10
fpga10
hdl10
checksum10
verilog9
sys9
compiler-compiler9
compiler9
embedded9
testbench8
testbed8
c-language7
Programming languages (7)
Github contributions (5)
Xilinx/finn
Apr 2022 - Jan 2023
Dataflow compiler for QNN inference on FPGAs
Role in this project:
Embedded Systems Engineer
Embedded Systems EngineerContributions:41 reviews, 45 commits, 34 PRs in 8 months
Contributions summary:Thomas implemented a checksum component and testbench within the repository, suggesting a focus on low-level data integrity. They developed a hardware design for checksum calculation over streaming data, incorporating features like subword slicing and coefficient re-alignment. Furthermore, the user created an AXI-Lite interface for accessing compiled-in information, indicating an understanding of hardware-software interaction within an FPGA context. The contributions point to hardware design and verification expertise related to dataflow processing.
compilerdataflowinferencequantizationfpga
VLSI-EDA/PoC
Dec 2014 - Jan 2020
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
Contributions:98 commits, 5 PRs, 69 pushes in 5 years 1 month
vhdlpoc-librarypythonsimulationsynthesis
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