Tiago Vidigal
Digital Projects Technical Leader at Chipus Microelectronics
Federal District, Brazil
Summary
👤
Senior🎓
Top SchoolTiago Vidigal is a Digital Projects Technical Leader with nine years of hands-on experience in digital IC design and verification, currently leading projects at Chipus Microelectronics. He specializes in SystemVerilog and UVM-based verification, integrating SystemC, Octave, and Python models via DPI to validate everything from communication IPs to complex DSP blocks. His work emphasizes test and quality, with practical use of SVA and UVM Register Layer and a growing interest in mixed-signal verification where he has developed exploratory test projects. Tiago combines frontend/backend ASIC flow experience with a strong academic grounding—a Master's in Software Engineering from Universidade de Brasília—and a history of teaching and training others in digital microelectronics. Not obvious from titles: he has repeatedly bridged high-level modeling and low-level silicon verification, making him effective at turning algorithmic models into verifiable hardware implementations. Based in Brazil’s Federal District, he brings both technical depth and a passion for improving verification practices across the IC lifecycle.
9 years of coding experience
Master, Software Engineering, Master, Software Engineering at Universidade de Brasília
Portuguese, English, Chinese
Github Skills (9)
midi3
converter2
music2
simulation1
audio1
python1
systemc1
modeling1
methodology1
Programming languages (3)
Github contributions (5)
TPVidigal/i2c_sadf
Jul 2018 - Nov 2018
Contributions:39 commits, 5 pushes in 4 months
wocame/AED-10-QAP
Mar 2021 - Mar 2021
Contributions:25 pushes in 24 days
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