Tianrui Wei
Staff Software Engineer at Fortinet
Berkeley, California, United States
Summary
🤩
Rockstar🎓
Top SchoolTianrui Wei is a Staff Software Engineer based in Berkeley with six years of engineering experience and a master's in Data Analytics Engineering from Northeastern University. He blends production software development with data analysis and revenue-management expertise, having driven double-digit RASM improvements earlier in his career at Hainan Airlines. At Fortinet he progressed from Software Engineer to Staff, building secure systems while contributing to notable open-source hardware tooling—migrating Rocket Chip code to Chisel3 and adding Slang SystemVerilog support to edalize. A quick learner and collaborative engineer, he focuses on backend reliability, formal verification areas, and test-driven integrations. His GitHub motto "tempus fugit" reflects a pragmatic, efficiency-minded approach to shipping durable, well-tested software.
6 years of coding experience
4 years of employment as a software developer
Master's degree, Data Analytics Engineering, Master's degree, Data Analytics Engineering at Northeastern UniversityBachelor's degree, Financial Engineering, Bachelor's degree, Financial Engineering at Hunan University
Chinese, English
Github Skills (16)
simulations10
rt10
simulation10
verilog10
systemverilog10
eda10
chisel10
scala10
testing9
python9
chip89
generator9
risc-v8
ghdl7
yosys7
Programming languages (11)
Github contributions (5)
chipsalliance/rocket-chip
Sep 2022 - Jan 2023
Rocket Chip Generator
Role in this project:
Backend Developer
Backend DeveloperContributions:32 reviews, 9 commits, 13 PRs in 3 months
Contributions summary:Tianrui primarily focused on converting and updating code within the Rocket Chip Generator repository. Their commits involved migrating codebases to Chisel3, a hardware description language. They specifically targeted areas such as formal verification, register mapping, and unit tests, indicating a focus on improving code compatibility and functionality within the project. Additionally, they contributed to refactoring other areas.
rtlriscvchipchiselscala
olofk/edalize
May 2021 - Aug 2021
An abstraction library for interfacing EDA tools
Role in this project:Software Engineer / SystemVerilog Developer
Software Engineer / SystemVerilog DeveloperContributions:6 commits, 1 PR, 6 comments in 3 months
Contributions summary:Tianrui primarily contributed to the edalize library by adding support for the Slang SystemVerilog frontend. Their work included implementing features like support for vlogparam, user-specified options, and addressing multiple definition issues. They also wrote and maintained tests related to the Slang integration, verifying linting and preprocessing functionality.
vivadovhdlxilinxsystemverilogsynthesis
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.