Tianyuan Xu
Design Verification Engineer
Ann Arbor, Michigan, United States
Summary
👤
Senior🎓
Top SchoolTianyuan Xu is a design verification engineer with 10 years of experience focused on logic design and verification, currently helping develop future-generation Ryzen cores at AMD. He has a strong track record in RTL verification, sign-off of IO port logic for automotive MCUs at Renesas, and mixed simulation workflows including VCS, Verdi coverage analysis, and low-power MVSIM techniques. Educated at the University of Michigan and the University of Edinburgh with top grades, he blends rigorous academic training with hands-on hardware and optical communications experience from industry roles. Colleagues would note his ability to translate complex design metrics into verifiable RTL acceptance criteria and his knack for finding subtle logic faults across large test suites.
10 years of coding experience
Bachelor's degree, Electrical and Electronics Engineering, 3.79/4.0, Bachelor's degree, Electrical and Electronics Engineering, 3.79/4.0 at The University of EdinburghMaster's degree, Electrical and Computer Engineering, 3.86/4.0, Master's degree, Electrical and Computer Engineering, 3.86/4.0 at University of MichiganBachelor's degree, Electrical and Electronics Engineering, 89.35/100, Bachelor's degree, Electrical and Electronics Engineering, 89.35/100 at North China Electric Power UniversityGithub contributions (4)
TianyuanXu/mysagecode
Sep 2015 - Apr 2017
Contributions:89 commits, 81 pushes, 1 branch in 1 year 6 months
TianyuanXu/vim
Jan 2016 - Mar 2017
Contributions:9 pushes, 1 branch in 1 year 2 months
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