Tim Newsome
Software Engineer at Nexthop AI
Seattle, Washington, United States
Summary
🤩
Rockstar🎓
Top SchoolTim Newsome is a seasoned software engineer with 11 years of professional experience and a deep background in embedded systems, debug, and development automation. He has driven tooling and test infrastructure at scale—from scaling Arista’s engineering tooling during rapid growth to leading the RISC-V Debug Specification and OpenOCD support at SiFive. Comfortable across C, C++, Python, Linux, and hardware interfaces (JTAG, logic analyzers, oscilloscopes), he combines low-level hardware debug skills with systems-oriented automation and tooling. His open-source contributions include performance-focused LuaUI and backend improvements to a real-time strategy game and critical fixes to the Spike RISC-V ISA simulator, reflecting a practical emphasis on correctness and performance. Based in Seattle with an MS and BS from Carnegie Mellon, he also experiments with full-stack side projects using Rust and Svelte, showing a continual appetite for learning and shipping end-to-end solutions.
11 years of coding experience
15 years of employment as a software developer
M.S. Electrical and Computer Engineering, M.S. Electrical and Computer Engineering at Carnegie Mellon University
Github Skills (15)
rt10
risc-v10
embedded10
lua10
c-language10
game-development10
cprogramming-language10
sys10
performance-optimization10
real-time-strategy10
debug9
debugging9
assemblies8
assembly8
assembler8
Programming languages (16)
Github contributions (5)
ZeroK-RTS/Zero-K
Sep 2020 - Apr 2021
Open source RTS game running on the Spring/Recoil engine
Role in this project:
Back-end Developer
Back-end DeveloperContributions:9 reviews, 57 commits, 4 PRs in 6 months
Contributions summary:Tim primarily focused on improving the efficiency and functionality of the game's LuaUI widgets. Their contributions included commenting on and removing unnecessary logging to improve performance, implementing a caching mechanism for metal resources, optimizing caretaker behavior to assist factories, and refining user command detection. The user's work demonstrates a focus on optimizing performance.
spring-bootgamertsspringjava
riscv-software-src/riscv-isa-sim
May 2024 - Mar 2025
Spike, a RISC-V ISA Simulator
Role in this project:Embedded Systems Engineer
Embedded Systems EngineerContributions:11 reviews, 7 PRs, 40 comments in 10 months
Contributions summary:Tim primarily focused on debugging and improving the RISC-V ISA simulator, Spike. Their contributions involved fixing issues related to trigger mechanisms, including mask operations, timing configurations, and interactions with the tcontrol register. The user also modified the code to handle cases where the tcontrol register doesn't exist and updated code related to privilege levels and trap handling. Overall, their work aimed at enhancing the functionality and correctness of the simulation environment.
risc-visariscvriscv32simulator
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.